The methods and structures disclosed herein relate to through-substrate vias (TSVs) for interconnecting chips in stacked-chip modules and, more particularly, to a method of forming a semiconductor chip with a dual damascene insulated wire and insulated TSV.
Stacked-chip modules (also referred to herein as stacked-chip packages, three-dimensional (3D) chip stacks or 3D multi-chip modules) have been developed to reduce form factor, interface latency and power consumption and to further increase in bandwidth. These benefits stem from the fact that, within a stacked-chip module, signals are passed through the chips using simple wire-based interconnects (e.g., through-substrate vias (TSVs) and micro-controlled collapsed chip connections (C4 connections)). TSVs are typically formed during back end of the line (BEOL) processing using a single damascene technique. Once the TSVs are formed, additional BEOL processing is performed to electrically connect the TSVs to on-chip devices. The BEOL processing steps used to form TSVs and subsequently electrically connect the TSVs to on-chip devices can be time-consuming and costly.